The present invention relates to integrated circuit products. More particularly, the invention is directed to refinements in a gate array type application specific integrated circuit which use gate isolation to separate field effect transistors into distinct functional groups.
Gate arrays are used extensively to fabricate integrated circuits which perform customer specialized functions, and as such are a subclass of products known as application specific integrated circuits (ASICs). The semiconductor devices of the gate arrays are designed into base patterns and fabricated into wafers for customer specific functional interconnection during metallization. Consequently, the integrated circuit semiconductor devices can be interconnected to perform the logic functions desired by a customer in the relatively short time needed to form the metallization patterns.
The metallization by which the pre-existing transistors and other active devices in the base set are interconnected to form functional configurations now preferably utilizes two or more metallization layers, a pattern of contacts to connect from the metallization layers to the semiconductor regions, and selectively defined vias to interconnect the successive metallization patterns.
The trend toward higher density and therefore greater functional capability in individual integrated circuit chips at lower levels of power consumption has led to the concurrent movement toward the use of complementary MOS (CMOS) devices configured from smaller active device cells.
Designing a gate array base set or pattern which maximizes the number of electronic functions performed on a semiconductor chip of defined areas is not merely a matter of shrinking field effect transistor dimensions. Integrated circuit design rules impose a number of constraints on the interconnection of the transistors. For example, the gate array design must satisfy minimum polysilicon width dimensions, minimum spacing between polysilicon conductors, minimum metal width dimensions, minimum spacing between metal conductors, minimum dimensions for contacts, minimum dimensions for vias, and constraints as to vertical placement of the various consecutive layers. Furthermore, the gate array technical community has yet to reach a consensus as to the optimum and preferred approach for maximizing functional density per unit area of semiconductor chip, with one end of the present spectrum preferring the "sea-of-gates" approach, in which the whole surface is covered with field effect transistors capable of being interconnected, and the other end of the present spectrum represented by gate arrays which use elongated patterns of field effect transistors separated by wide wiring channel regions nominally twice the area of the transistor regions.
A relatively recent refinement in the design of gate arrays has been the introduction of gate isolation. According to this technology, a chain of field effect transistors, often individually referred to as gates or cells, is defined in the substrate with the source region of one serving as the drain region of the other in a continuum separated only by successive gate electrodes with underlying channel regions. Electrical isolation of active transistors is accomplished by tying the gate electrodes of the peripheral transistors to the power supply or the ground potential, respectively for the p-channel and n-channel devices. The interconnection as well as the tying is performed during metallization. Connection of the gates to perform isolation and electronic functions is preferably undertaken with computer aided design equipment in response to functional descriptions entered by a circuit designer.
Representative gate isolation type gate array technologies appear in U.S. Pat. Nos. 4,745,084; 4,570,176; 4,633,571; and 4,562,453; are described in the Mar. 21, 1988 issue of Electronic News; and are considered in the article by Meyer entitled "Garnering the Gates in High-Density Arrays" as appeared in VLSI Systems Design-Semicustom Design Guide--1988 on pages 8-20.
Gate array and standard cell arrangements which incorporate channels for interconnection are the subjects of the U.S. Pat. Nos. 4,161,662 and 4,661,815. However, neither reference attempts to define an optimum channel to transistors area ratio. U.S. Pat. No. 4,549,131 involves the use of crossunder diffusions, which are situated in gate array wiring channels, for resistor elements in gate array designs.
There remains the need for a high density gate array architecture using a channel based CMOS gate isolated configuration which has the transistor gate electrode pitch and metallization pitch relatively coincide while permitting full contact formation to both substrate and gate polysilicon, and which further includes an optimized channel width to maximize the functions implemented per unit area of a semiconductor chip.